1. Field of the Invention
The present invention relates to an asymmetry thin-film transistor (TFT), and more particularly, to an asymmetry thin-film transistor in a liquid crystal display.
2. Description of the Prior Art
From the fact that a thin-film transistor having an active layer formed of a crystalline silicon film on a substrate having an insulating surface has a high electric field effect mobility, it is possible to form a variety of functional circuits. For example, in the active matrix liquid crystal device (AMLCD) employing the crystalline silicon thin-film transistor, a thin-film transistor used as a pixel switch is formed in every pixel of an imaged is play region, and a thin-film transistor used in a drive circuit is formed in the periphery of the image display region.
Since the functions and the operating conditions of the thin-film transistors in the pixel and the drive circuit are not the same, the characteristics that are demanded for a thin-film transistor is somewhat different. For example, the pixel thin-film transistor is demanded to function as a switch device for applying a voltage to a liquid crystal, so as to control the rotation angle of the liquid crystal. In this case, the characteristic that is demanded for the pixel thin-film transistor was to sufficiently lower an off-current value (a drain current that flows during an off-operation of the thin-film transistor), so as to maintain sufficient electric charges in a pixel storage capacitor.
Please refer to FIG. 1 of a cross-sectional diagram of a thin-film transistor according to the prior art. A thin-film transistor 10 includes a substrate 12, a semiconductor layer 14 positioned on the substrate 12, a gate insulating layer 16 positioned on the semiconductor layer 14, and a gate 18 positioned on the gate insulating layer 16. The semiconductor layer 14 includes two symmetric lightly doped drains (LDD) 20 and 22 and two symmetric source/drain regions 24 and 26 adjacent to the gate 18. A channel region 28 is defined between the lightly doped drain 20 and the lightly doped drain 22.
The lightly doped drains 20 and 22 are formed of n-type dopants to reduce leakage currents of the thin-film transistor, and prevent the electric field around the drain from getting too high to bring hot electron effects. Having lower dopant densities, the resistance of the lightly doped drains 20 and 22 is usually higher than the resistance of the source/drain regions 24 and 26. Therefore, the series resistance between the drain and the source 24, 26 is increased to reduce the electron mobility and the device operation speeds with the insertion of the lightly doped drains 20 and 22. In this case, the device operation speeds have to be sacrificed when using the lightly doped drains to solve the leakage current problems. Therefore, how to value the characteristics of the electron mobility and the leakage current values has become an important issue in the design and the fabrication of the lightly doped drains.
Please refer to FIG. 2 to FIG. 5 of schematic diagrams to respectively illustrate correlations of an LDD length with a threshold voltage, electron mobility and a leakage current value (including an off-current Ioff measured during an off-operation or a drain current Id measured during a reverse-bias operation) of a thin-film transistor. As shown in these diagrams, when a length of the lightly doped drains 20 and 22 increases from 0 to 3 micrometers (μm), a threshold voltage increases, electron mobility reduces, and a leakage current value (Ioff or Id) reduces. It is obvious that one cannot keep high electron mobility and reduce leakage currents at the same time. Therefore, it is difficult to improve the device performances effectively.